module mux2 (
    D_in0,
    D_in1,
    date_out
    sel,
    en);
    input [15:0] D_in0;
    input [15:0] D_in1;
    input sel;
    input en;
    output reg [15:0] date_out;
    always @(*) begin
        if (!en) 
            date_out = 'b0;
        else 
            case (sel)
                1'b0: date_out = D_in0; 
                1'b1: date_out = D_in1;
            endcase    
    end
endmodule
